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connection diagram ad549 offset null output nc v offset null noninverting input 6 7 1 3 4 5 2 8 v+ guard pin, connected to case inverting input 1 4 5 v os trim ?5v 10k w nc = no connection rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ultralow input bias current operational amplifier ad549* one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features ultralow bias current: 60 fa max (ad549l) 250 fa max (ad549j) input bias current guaranteed over common-mode voltage range low offset voltage: 0.25 mv max (ad549k) 1.00 mv max (ad549j) low offset drift: 5 m v/ 8 c max (ad549k) 20 m v/ 8 c max (ad549j) low power: 700 m a max supply current low input voltage noise: 4 m v p-p 0.1 hz to 10 hz mil-std-883b parts available applications electrometer amplifiers photodiode preamp ph electrode buffer vacuum lon gage measurement product description the ad549 is a monolithic electrometer operational amplifier with very low input bias current. input offset voltage and input offset voltage drift are laser trimmed for precision performance. the ad549s ultralow input current is achieved with topgate jfet technology, a process development exclusive to analog devices. this technology allows the fabrication of extremely low input current jfets compatible with a standard junction- isolated bipolar process. the 10 15 w common-mode impedance, a result of the bootstrapped input stage, insures that the input current is essentially independent of common-mode voltage. the ad549 is suited for applications requiring very low input current and low input offset voltage. it excels as a preamp for a wide variety of current output transducers such as photodiodes, photomultiplier tubes, or oxygen sensors. the ad549 can also be used as a precision integrator or low droop sample and hold. the ad549 is pin compatible with standard fet and electrom- eter op amps, allowing designers to upgrade the performance of present systems at little additional cost. the ad549 is available in a to-99 hermetic package. the case is conne cted to pin 8 so that the metal case can be indepen dently connected to a point at the same potential as the input termi- nals, minimizing stray leakage to the case. *protected by patent no. 4,639,683. the ad549 is available in four performance grades. the j, k, and l versions are rated over the commercial temperature range 0 c to +70 c. the s grade is specified over the military tem- perature range of C55 c to +125 c and is available processed to mil-std-883b, rev c. extended reliability plus screening is also available. plus screening includes 168-hour burn-in, as well as other environmental and physical tests derived from mil-std-883b, rev c. product highlights 1. the ad549s input currents are specified, 100% tested and guaranteed after the device is warmed up. input current is guaranteed over the entire common-mode input voltage range. 2. the ad549s input offset voltage and drift are laser trimmed to 0.25 mv and 5 m v/ c (ad549k), 1 mv and 20 m v/ c (ad549j). 3. a maximum quiescent supply current of 700 m a minimizes heating effects on input current and offset voltage. 4. ac specifications include 1 mhz unity gain bandwidth and 3 v/ m s slew rate. settling time for a 10 v input step is 5 m s to 0.01%. 5. the ad549 is an improved replacement for the ad515, opa104, and 3528.
ad549Cspecifications model ad549j ad549k ad549l ad549s min typ max min typ max min typ max min typ max units input bias current 1 either input, v cm = 0 v 150 250 75 100 40 60 75 100 fa either input, v cm = 10 v 150 250 75 100 40 60 75 100 fa either input at t max , v cm = 0 v 11 4.2 2.8 420 pa offset current 50 30 20 30 fa offset current at t max 2.2 1.3 0.85 125 pa input offset voltage 2 initial offset 0.5 1.0 0.15 0.25 0.3 0.5 0.3 0.5 mv offset at t max 1.9 0.4 0.9 2.0 mv vs. temperature 10 20 2 5 5 10 10 15 m v/ c vs. supply 32 100 10 32 10 32 10 32 m v/v vs. supply, t min to t max 32 100 10 32 10 32 32 50 m v/v long-term offset stability 15 15 15 15 m v/month input voltage noise f = 0.1 hz to 10 hz 4 4 6 44 m v p-p f = 10 hz 90 90 90 90 nv/ ? hz f = 100 hz 60 60 60 60 nv/ ? hz f = 1 khz 35 35 35 35 nv/ ? hz f = 10 khz 35 35 35 35 nv/ ? hz input current noise f = 0.1 hz to 10 hz 0.7 0.5 0.36 0.5 fa rms f = 1 khz 0.22 0.16 0.11 0.16 fa/ ? hz input impedance differential v diff = 110 13 i 110 13 i 110 13 i 110 13 i 1 w i pf common mode v cm = 10 10 15 i 0.8 10 15 i 0.8 10 15 i 0.8 10 15 i 0.8 w i pf open-loop gain v o @ 10 v, r l = 10 k 300 1000 300 1000 300 1000 300 1000 v/mv v o @ 10 v, r l = 10 k, t min to t max 300 800 300 800 300 800 300 800 v/mv v o = 10 v, r l = 2 k 100 250 100 250 100 250 100 250 v/mv v o = 10 v, r l = 2 k, t min to t max 80 200 80 200 80 200 25 150 v/mv input voltage range differential 3 20 20 20 20 v common-mode voltage C10 +10 C10 +10 C10 +10 C10 +10 v common-mode rejection ratio v = +10 v, C10 v 80 90 90 100 90 100 90 100 db t min to t max 76 80 80 90 80 90 80 90 db output characteristics voltage @ r l = 10 k, t min to t max C12 +12 C12 +12 C12 +12 C12 +12 v voltage @ r l = 2 k, t min to t max C10 +10 C10 +10 C10 +10 C10 +10 v short circuit current 15 20 35 15 20 35 15 20 35 15 20 35 ma t min to t max 9996 ma load capacitance stability g = +1 4000 4000 4000 4000 pf frequency response unity gain, small signal 0.7 1.0 0.7 1.0 0.7 1.0 0.7 1.0 mhz full power response 50 50 50 50 khz slew rate 2 3 2 3 2 3 2 3 v/ m s settling time, 0.1% 4.5 4.5 4.5 4.5 m s 0.01%5555 m s overload recovery, 50% overdrive, g = C1 2222 m s (@ +25 8 c and v s = +15 v dc, unless otherwise noted) rev. a C2C
model ad549j ad549k ad549l ad549s min typ max min typ max min typ max min typ max units power supply rated performance 15 15 15 15 v operating 6 5 6 18 6 5 6 18 6 5 6 18 6 5 6 18 v quiescent current 0.60 0.70 0.60 0.70 0.60 0.70 0.60 0.70 ma temperature range operating, rated performance 0 +70 0 +70 0 +70 C55 +125 c storage C65 +150 C65 +150 C65 +150 C65 +150 c package option to-99 (h-08a) ad549jh ad549kh ad549lh ad549sh, ad549sh/883b chips ad549jchips notes 1 bias current specifications are guaranteed after 5 minutes of operation at t a = +25 c. bias current increases by a factor of 2.3 for every 10 c rise in temperature. 2 input offset voltage specifications are guaranteed after 5 minutes of operation at t a = +25 c. 3 defined as max continuous voltage between the inputs such that neither input exceeds 10 v from ground. specifications subject to change without notice. all min and max specifications are guaranteed. specifications in boldface are tested on all production units at final electrical test. results from those tests are used to calculate outgoing quality levels. metalization photograph dimensions shown in inches and (mm). contact factory for latest dimensions. absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation . . . . . . . . . . . . . . . . . . . . . . 500 mw input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v 2 output short circuit duration . . . . . . . . . . . . . . . . . indefinite differential input voltage . . . . . . . . . . . . . . . . . . +v s and Cv s storage temperature range (h) . . . . . . . . . . C65 c to +125 c operating temperature range ad549j (k, l) . . . . . . . . . . . . . . . . . . . . . . . . 0 c to +70 c ad549s . . . . . . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c lead temperature range (soldering 60 sec) . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 for supply voltages less than 18 v, the absolute maximum input voltage is equal to the supply voltage. ad549 rev. a C3C warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad549 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad549Ctypical characteristics supply voltage v input voltage v 20 15 10 5 0 0 5 10 15 20 +v in ? in figure 1. input voltage range vs. supply voltage supply voltage v 800 700 600 500 400 amplifier quiescent current ?? 0 5 10 15 20 figure 4. quiescent current vs. supply voltage temperature ? c 3000 open-loop gain ?v/mv ?5 ?5 5 35 65 95 125 1000 300 100 figure 7. open-loop gain vs. temperature supply voltage v 20 15 10 5 0 output voltage swing v 0 5 10 15 20 +v out ? out +25 c r l = 10k figure 2. output voltage swing vs. supply voltage input common-mode voltage ?v 120 100 90 80 70 common-mode rejection ratio ?db ?5 ?0 0 +10 +15 110 figure 5. cmrr vs. input common-mode voltage warm-up time ?minutes 30 d |v os | ?? 0 1 2 3 4 5 6 7 25 20 15 10 5 0 figure 8. change in offset voltage vs. warm-up time load resistance ? w 30 25 20 10 0 10 100 1k 10k 100k 5 15 output voltage swing ?volts p-p v s = 15 volts figure 3. output voltage swing vs. load resistance supply voltage v 3000 open-loop gain ?v/mv 0 5 10 15 20 1000 300 100 figure 6. open-loop gain vs. supply voltage common-mode voltage v 50 input current ?fa ?0 ? 0 5 10 40 35 20 30 25 45 figure 9. input bias current vs. common-mode voltage rev. a C4C
ad549 rev. a C5C power supply voltage v 50 input current ?fa 0 5 10 15 20 40 35 20 30 25 45 figure 10. input bias current vs. supply voltage frequency ?hz 100 80 60 40 ?0 open loop gain ?db 10 100 1k 10k 100k 1m 10m 20 0 ?0 100 80 60 40 ?0 20 0 ?0 phase margin ? figure 13. open-loop frequency response frequency ?hz 160 140 120 80 40 10 100 1k 10k 60 100 noise spectral density ?nv/ ? hz 20 figure 11. input voltage noise spectral density output voltage swing ?v frequency ?hz 40 35 30 20 10 10 100 1k 10k 100k 1m 15 25 5 0 figure 14. large signal frequency response source resistance ? w 100k input noise voltage ?? p-p 100k 1m 10m 100m 1g 10g 100g 1k 100 0.1 10 1 10k resistor johnson noise whenever johnson noise is greater than amplifier noise, amplifier noise can be considered negligible for the application 1khz bandwidth 10hz bandwidth amplifier generated noise figure 12. noise vs. source resistance frequency ?hz 100 80 60 40 cmrr ?db 10 100 1k 10k 100k 1m 10m 20 0 ?0 figure 15. cmrr vs. frequency frequency ?hz 120 100 80 60 ?0 psrr ?db 10 100 1k 10k 100k 1m 10m 40 20 0 + supply ?supply figure 16. psrr vs. frequency settling time ?? 10 5 0 ? ?0 output voltage swing ?v 0 1 2 3 4 5 5mv 10mv 1mv 1mv 5mv 10mv figure 17. output voltage swing and error vs. settling time
ad549 rev. a C6C figure 18. unity gain follower figure 21. unity gain inverter figure 19. unity gain follower large signal pulse response figure 22. unity gain inverter large signal pulse response figure 20. unity gain follower small signal pulse response figure 23. unity gain inverter small signal pulse response minimizing input current the ad549 has been optimized for low input current and offset voltage. careful attention to how the amplifier is used will reduce input currents in actual applications. the amplifier operating temperature should be kept as low as pos- sible to minimize input current. like other jfet input amplifiers, the ad549s input current is sensitive to chip temperature, rising by a factor of 2.3 for every 10 c rise. this is illustrated in figure 24, a plot of ad549 input current versus ambient temperature. temperature ? c 1na 100pa 10pa 1fa ?5 ?5 5 35 65 95 125 1pa 100fa 10fa figure 24. ad549 input bias current vs. ambient temperature on-chip power dissipation will raise chip operating temperature causing an increase in input bias current. due to the ad549s low quiescent supply current, chip temperature when the (un- loaded) amplifier is operated with 15 v supplies, is less than 3 c higher than ambient. the difference in input current is negligible. however, heavy output loads can cause a significant increase in chip temperature and a corresponding increase in input current. maintaining a minimum load resistance of 10 w is rec- ommended. input current versus additional power dissipation due to output drive current is plotted in figure 25. additional internal power dissipation ?mw 6.0 5.0 4.0 1.0 0 25 50 75 100 125 150 175 200 3.0 2.0 normalized input bias current based on typical i b = 40fa figure 25. ad549 input bias current vs. additional power dissipation circuit board notes there are a number of physical phenomena that generate spurious currents that degrade the accuracy of low current measurements. figure 26 is a schematic of an i-to-v converter with these parasitic currents modeled. finite resistance from input lines to voltages on the board, modeled by resistor r p , results in parasitic leakage. insulation resistance of over 10 15 w must be maintained between the amplifiers signal and supply lines in order to capitalize on the ad549s low input currents. standard pc board material
ad549 rev. a C7C mized. input capacitance can substantially degrade signal band- width and the stability of the i-to-v converter. the case of the ad549 is connected to pin 8 so that it can be bootstrapped near the input potential. this minimizes pin leakage and input common-mode capacitance due to the case. guard schemes for inverting and noninverting amplifier topologies are illustrated in figures 28 and 29. figure 28. inverting amplifier with guard figure 29. noninverting amplifier with guard other guidelines include keeping the circuit layout as compact as possible and input lines short. keeping the assembly rigid and minimizing sources of vibration will reduce triboelectric and piezoelectric effects. all precision high impedance circuitry re- quires shielding against interference noise. low noise coax or triax cables should be used for remote connections to the input signal lines. offset nulling the ad549s input offset voltage can be nulled by using balance pins 1 and 5, as shown in figure 30. nulling the input offset voltage in this fashion will introduce an added input offset volt- age drift component of 2.4 m v/ c per millivolt of nulled offset (a maximum additional drift of 0.6 m v/ c for the ad549k, 1.2 m v/ c for the ad549l, 2.4 m v/ c for the ad549j). figure 30. standard offset null circuit the approach in figure 31 can be used when the amplifier is used as an inverter. this method introduces a small voltage referenced to the power supplies in series with the amplifiers does not have high enough insulation resistance. therefore, the ad549s input leads should be connected to standoffs made of insulating material with adequate volume resistivity (e.g., teflon*). the surface of the insulators surface must be kept clean in order to preserve surface resistivity. for teflon, an ef- fective cleaning procedure consists of swabbing the surface with high-grade isopropyl alcohol, rinsing with deionized water, and baking the board at 80 c for 10 minutes. figure 26. sources of parasitic leakage currents in addition to high volume and surface resistivity, other proper- ties are desirable in the insulating material chosen. resistance to water absorption is important since surface water films drasti- cally reduce surface resistivity. the insulator chosen should also exhibit minimal piezoelectric effects (charge emission due to mechanical stress) and triboelectric effects (charge generated by friction). charge imbalances generated by these mechanisms can appear as parasitic leakage currents. these effects are modeled by variable capacitor c p in figure 26. the table in figure 27 lists various insulators and their properties. 1 volume minimal minimal resistance resistivity triboelectric piezoelectric to water material ( v Ccm) effects effects absorption teflon* 10 17 C10 18 wwg kel-f** 10 17 C10 18 wmg sapphire 10 16 C10 18 mgg polyethylene 10 14 C10 18 mgm polystyrene 10 12 C10 18 wmm ceramic 10 12 C10 14 wmw glass epoxy 10 10 C10 17 wmw pvc 10 10 C10 15 gmg phenolic 10 5 C10 12 wg w gCgood with regard to property mCmoderate with regard to property wCweak with regard to property figure 27. insulating materials and characteristics guarding the input lines by completely surrounding them with a metal conductor biased near the input lines potential has two major benefits. first, parasitic leakage from the signal line is reduced since the voltage between the input line and the guard is very low. second, stray capacitance at the input node is mini- 1 electronic measurements, pp. 15C17, keithley instruments, inc., cleveland, ohio, 1977. *teflon is a registered trademark of e.i. dupont co. **kel-f is a registered trademark of 3-m company.
ad549 rev. a C8C positive input terminal. the amplifiers input offset voltage drift with temperature is not affected. however, variation of the power supply voltages will cause offset shifts. figure 31. alternate offset null circuit for inverter ac response with high value source and feedback resistance source and feedback resistances greater than 100 k w will mag- nify the effect of input capacitances (stray and inherent to the ad549) on the ac behavior of the circuit. the effects of common-mode and differential input capacitances should be taken into account since the circuits bandwidth and stability can be adversely affected. figure 32. follower pulse response from 1 m w source resistance, case not bootstrapped figure 33. follower pulse response from 1 m w source resistance, case bootstrapped in a follower, the source resistance and input common-mode capacitance form a pole that limits the bandwidth to 1/2 p r s c s . bootstrapping the metal case by connecting pin 8 to the output minimizes capacitance due to the package. figures 32 and 33 show the follower pulse response from a 1 m w source resistance with and without the package connected to the output. typical common-mode input capacitance for the ad549 is 0.8 pf. in an inverting configuration, the differential input capacitance forms a pole in the circuits loop transmission. this can create peaking in the ac response and possible instability. a feedback capacitance can be used to stabilize the circuit. the inverter pulse response with r f and r s equal to 1 m w appears in figure 34. figure 35 shows the response of the same circuit with a i pf feedback capacitance. typical differential input capacitance for the ad549 is 1 pf. common-mode input voltage overload the rated common-mode input voltage range of the ad549 is from 3 v less than the positive supply voltage to 5 v greater than the negative supply voltage. exceeding this range will de- grade the a mplifiers cmrr. driving the common-mode voltage above the positive supply will cause the amplifiers output to saturate at the upper limit of output voltage. recovery time is typically 2 m s after the input has been returned to within the nor- mal operating range. driving the input common-mode voltage within 1 v of the negative supply causes phase reversal of the output signal. in this case, normal operation is typically resumed within 0.5 m s of the input voltage returning within range. figure 34. inverter pulse response with 1 m w source and feedback resistance figure 35. inverter pulse response with 1 m w source and feedback resistance, 1 pf feedback capacitance differential input voltage overload a plot of the ad549s input currents versus differential input voltage (defined as v in + Cv in C) appears in figure 36. the input current at either terminal stays below a few hundred femtoamps until one input terminal is forced higher than 1 v to 1.5 v above the other terminal. under these conditions, the input current limits at 30 m a.
ad549 rev. a C9C differential input voltage ?v (v in ? ?v in ) 100 10 1 ? ? ? ? ? 0 1 2 3 4 5 input current ?amps 100n 10n 1n 100p 10p 1p 100f 10f i in i in + figure 36. input current vs. differential input voltage input protection the ad549 safely handles any input voltage within the supply voltage range. subjecting the input terminals to voltages beyond the power supply can destroy the device or cause shifts in input current or offset voltage if the amplifier is not protected. a protection scheme for the amplifier as an inverter is shown in figure 37. r p is chosen to limit the current through the invert- ing input to 1 ma for expected transient (less than 1 second) overvoltage conditions, or to 100 m a for a continuous overload. since r p is inside the feedback loop, and is much lower in value than the amplifiers input resistance, it does not affect the inverters dc gain. however, the johnson noise of the resistor will add root sum of squares to the amplifiers input noise. figure 37. inverter with input current limit in the corresponding version of this scheme for a follower, shown in figure 38, r p and the capacitance at the positive input terminal will produce a pole in the signal frequency response at a f = 1/2 p rc. again, the johnson noise r p will add to the amplifiers input voltage noise. figure 38. follower with input current limit figure 39 is a schematic of the ad549 as an inverter with an input voltage clamp. bootstrapping the clamp diodes at the in- verting input minimizes the voltage across the clamps and keeps the leakage due to the diodes low. low leakage diodes, such as the fd333s should be used, and should be shielded from light to keep photocurrents from being generated. even with these precautions, the diodes will measurably increase the input cur- rent and capacitance. figure 39. input voltage clamp with diodes sample and difference circuit to measure electrometer leakage currents there are a number of methods used to test electrometer leak- age currents, including current integration and direct current to voltage conversion. regardless of the method used, board and interconnect cleanliness, proper choice of insulating materials (such as teflon or kel-f), correct guarding and shielding tech- niques and care in physi-cal layout are essential to making accu- rate leakage measurements. figure 40 is a schematic of the sample and difference circuit. it uses two ad549 electrometer amplifiers (a and b) as current-to voltage converters with high value (10 10 w ) sense resistors (rsa and rsb). r1 and r2 provide for an overall circuit sensitivity of 10 fa/mv (10 pa full scale). c c and c f provide noise suppres- sion and loop compensation. c c should be a low leakage poly- styrene capacitor. an ultralow leakage kel-f test socket is used for contacting the device under test. rigid teflon coaxial cable is used to make connections to all high impedance nodes. the figure 40. sample and difference circuit for measuring electrometer leakage currents
ad549 rev. a C10C use of rigid coax affords immunity to error induced by mechani- cal vibration and provides an outer conductor for shielding. the entire circuit is enclosed in a grounded metal box. the test apparatus is calibrated without a device under test present. a five minute stabilization period after the power is turned on is required. first, v err1 and v err2 are measured. these voltages are the errors caused by offset voltages and leak- age currents of the current to voltage converters. v err 1 = 10 ( v os a C i b a rsa ) v err 2 = 10 ( v os b C i b b rsb ) once measured, these errors are subtracted from the readings taken with a device under test present. amplifier b closes the feedback loop to the device under test, in addition to providing current to voltage conversion. the offset error of the device un- der test appears as a common-mode signal and does not affect the test measurement. as a result, only the leakage current of the device under test is measured. v a C v err 1 = 10[ rsa i b (+)] v x C v err2 = 10[rsb i b (C)] although a series of devices can be tested after only one calibra- tion measurement, calibration should be updated periodically to compensate for any thermal drift of the current to voltage con- verters or changes in the ambient environment. laboratory re- sults have shown that repeatable measurements within 10 fa can be realized when this apparatus is properly implemented. these results are achieved in part by the design of the circuit, which eliminates relays and other parasitic leakage paths in the high impedance signal lines, and in part by the inherent cancellation of errors through the calibration and measurement procedure. photodiode interface the ad549s low input current and low input offset voltage make it an excellent choice for very sensitive photodiode preamps (figure 41). the photodiode develops a signal current, i s equal to: i s = r p where p is light power incident on the diodes surface in watts and r is the photodiode responsivity in amps/watt. r f converts the signal current to an output voltage: v out = r f i s figure 41. photodiode preamp dc error sources and an equivalent circuit for a small area (0.2 mm square) photodiode are indicated in figure 42. figure 42. photodiode preamp dc error sources input current, i b , will contribute an output voltage error, v e1 , proportional to the feedback resistance: v e 1 = i b r f the op amps input voltage offset will cause an error current through the photodiodes shunt resistance, r s : i = v os / r s the error current will result in an error voltage (v e2 ) at the amplifiers output equal to: v e 2 = ( i + r f / r s ) v os given typical values of photodiode shunt resistance (on the order of 10 9 w ), r f /r s can easily be greater than one, especially if a large feedback resistance is used. also, r f /r s will increase with temperature, as photodiode shunt resistance typically drops by a factor of two for every 10 c rise in temperature. an op amp with low offset voltage and low drift must be used in order to maintain accuracy. the ad549k offers guaranteed maximum 0.25 mv offset voltage, and 5 mv/ c drift for very sensitive applications. photodiode preamp noise noise limits the signal resolution obtainable with the preamp. the output voltage noise divided by the feedback resistance is the minimum current signal that can be detected. this mini- mum detectable current divided by the responsivity of the pho- todiode represents the lowest light power that can be detected by the preamp. noise sources associated with the photodiode, amplifier, and feedback resistance are shown in figure 43; figure 44 is the spectral density versus frequency plot of each of the noise sources contribution to the output voltage noise (circuit param- eters in figure 42 are assumed). each noise sources rms contri- bution to the total output voltage noise is obtained by integrating the square of its spectral density function over frequency. the rms value of the output voltage noise is the square root of the sum of all contributions. minimizing the total area under these curves will op- timize the preamplifiers resolution for a given bandwidth. the photodiode preamp in figure 41 can detect a signal current of 26 fa rms at a bandwidth of 16 hz, which assuming a photo- diode responsivity of 0.5 a/w, translates to a 52 fw rms mini- mum detectable power. the photodiode used has a high source resistance and low junction capacitance. c f sets the signal band- width with r f and also limits the peak in the noise gain that multiplies the op amps input voltage noise contribution. a single pole filter at the amplifiers output limits the op amps out- put voltage noise b andwidth to 26 hz, a freq uency comparable to the signal bandwidth. this greatly improves the preamplifiers signal to noise ratio (in this case, by a factor of three).
ad549 rev. a C11C figure 43. photodiode preamp noise sources figure 44. photodiode preamp noise sources spectral density vs. frequency log ratio amplifier logarithmic ratio circuits are useful for processing signals with wide dynamic range. the ad549ls 60 fa maximum input cur- rent makes it possible to build a log ratio amplifier with 1% log conformance for input current ranging from 10 pa to 1 ma, a dynamic range of 160 db. the log ratio amplifier in figure 45 provides an output voltage proportional to the log base 10 of the ratio of the input currents i1 and i2. resistors r1 and r2 are provided for voltage inputs. since npn devices are used in the feedback loop of the front- end amplifiers that provide the log transfer function, the output is valid only for positive input voltages and input currents. the input currents set the collector currents ic1 and ic2 of a matched pair of log transistors q1 and q2 to develop voltages va and vb: va, b = C ( kt / q ) ln ic / ies where ies is the transistors saturation current. the difference of va and vb is taken by the subtractor section to obtain: vc = (kt/ q ) ln ( ic 2/ ic 1) vc is scaled up by the ratio of (r9 + r10)/r8, which is equal to approximately 16 at room temperature, resulting in the output voltage: v out = 1 log ( ic 2/ ic 1) v . r8 is a resistor with a positive 3500 ppm/ c temperature coeffi- cient to provide the necessary temperature compensation. the parallel combination of r15 and r7 is provided to keep the sub tracter sections gain for positive and negative inputs matched over temperature. frequency compensation is provided by r11, r12, and c1 and c2. the bandwidth of the circuit is 300 khz at input signals greater than 50 m a, and decreases smoothly with decreasing signal levels. to trim the circuit, set the input currents to 10 m a and trim a3s offset using the amplifiers trim potentiometer so the out- put equals 0. then set i1 to 1 m a and adjust the output to equal 1 v by trimming r10. additional offset trims on the amplifiers a1 and a2 can be used to increase the voltage input accuracy and dynamic range. the very low input current of the ad549 makes this circuit use- ful over a very wide range of signal currents. the total input current (which determines the low level accuracy of the circuit) is the sum of the amplifier input current, the leakage across the compensating capacitor (negligible if polystyrene or teflon ca- pacitor is used), and the collector to collector, and collector to base leakages of one side of the dual log transistors. the magni- tude of these last two leakages depend on the amplifiers input offset voltage and are typically less than 10 fa with 1 mv offsets. the low level accuracy is limited primarily by the amplifiers in- put current, only 60 fa maximum when the ad549l is used. figure 45. log ratio amplifier the effects of the emitter resistance of q1 and q2 can degrade the circuits accuracy at input currents above 100 m a. the net- works composed of r13, d1, r16, and r14, d2, r17 compen- sate for these errors, so that this circuit has less than 1% log conformance error at 1 ma input currents. the correct value for r13 and r14 depends on the type of log transistors used. 49.9 k w resistors were chosen for use with lm394 transistors. smaller resistance values will be needed for smaller log transistors.
ad549 rev. a C12C the ph probe output is ideally zero volts at a ph of 7 indepen- dent of temperature. the slope of the probes transfer function, though predictable, is temperature dependent (C54.2 mv/ph at 0 and C74.04 mv/ph at 100 c). by using an ad590 tempera- ture sensor and an ad535 analog divider, an accurate tempera- ture compensation network can be added to the basic ph probe amplifier. the table in figure 47 shows voltages at various points and i llustrates the compensation. the ad549 is set for a nonin- verting gain of 13.51. the output of the ad590 circuitry (point c) will be equal to 10 v at 100 c and decrease by 26.8 mv/ c. the output of the ad535 analog divider (point d) will be a temperature compensated output voltage centered at zero volts for a ph of 7, and having a transfer function of C1.00 v/ph unit. the output range spans from C7.00 v (ph = 14) to +7.00 v (ph = 0). p robe a b c d temp (probe output) (a 3 13.51) (590 output) (10 b/c) 0 54.20 mv 0.732 v 7.32 v 1.00 v 25 8 c 59.16 mv 0.799 v 7.99 v 1.00 v 37 8 c 61.54 mv 0.831 v 8.31 v 1.00 v 60 8 c 66.10 mv 0.893 v 8.93 v 1.00 v 100 8 c 74.04 mv 1.000 v 10.00 v 1.00 v figure 47. table illustrating temperature compensation temperature compensated ph probe amplifier a ph probe can be modeled as a mv-level voltage source with a series source resistance dependent upon the electrodes compo- sition and configuration. the glass bulb resistance of a typical ph electrode pair falls between 10 6 and 10 9 w . it is therefore important to select an amplifier with low enough input currents such that the voltage drop produced by the amplifiers input bias current and the electrode resistance does not become an appreciable percentage of a ph unit. the circuit in figure 46 illustrates the use of the ad549 as a ph probe amplifier. as with other electrometer applications, the use of guarding, shielding, teflon standoffs, etc., is a must in order to capitalize on the ad549s low input current. if an ad549l (60 fa max input current) is used, the error contrib- uted by input current will be held below 60 m v for ph electrode source impedances up to 10 9 w . input offset voltage (which can be trimmed) will be below 0.5 mv. figure 46. temperature compensated ph probe amplifier c1073aC10C10/87 printed in u.s.a. outline dimensions dimensions shown in inches and (mm). to-99 (h) package 0.045 (1.1) 0.020 (0.51) 0.034 (0.86) 0.028 (0.41) 1 3 5 0.2 (5.1) typ 2 4 6 7 8 45?equally spaced bottom view seating plane 0.019 (0.48) 0.016 (0.41) 0.335 (8.50) 0.305 (7.75) 0.370 (9.40) 0.335 (8.50) 0.500 (12.70) min 0.040 (1.0) max 0.185 (4.70) 0.165 (4.19) 8 leads dia insulation 0.05 (1.27) max refference plane

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